Robust sub-100 nm T-Gate fabrication process using multi-step development

We demonstrate the fabrication of sub-100 nm T-Gate structures using a single electron beam lithography exposure and tri-layer resist stack - PMMA/LOR/CSAR. Recent developments in modelling development were used to design process, which each is developed separately optimise resulting structure. By approach proximity correcting for full stack, we able independently vary gate length (50-100 nm) head size (250-500 at stage fabricate these T-Gates with high yield.